In a memory, such as for example an SRAM (Static Random Access Memory), the CLK2Q (clock-to-data) time may vary across process corners. Utilizing a dummy word line connected to a dummy row cell pulldown with a dummy bit line is an approach to tracking variations in CLK2Q to improve read and write margins, where a controller enables reading of the bitlines based upon the dummy bitline being pulled LOW on a write or read operation. However, this approach does not always meet the desired write margin for a SF (Slow-Fast) process corner where nMOSFETs (Metal Oxide Semiconductor Field Effect Transistor) are slow and pMOSFETs are fast.